1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, relates to a semiconductor memory device capable of generating a delay signal.
2. Description of the Related Art
A semiconductor memory device is provided with a delay circuit. A delay amount by the delay circuit is determined through simulation at the time of designing. However, an actual delay amount by the delay circuit is different from the that of the delay circuit at the time of designing, due to diffusion conditions, in-plane variations in a wafer, and so on, at the time of manufacturing a semiconductor memory device.
It is desired to eliminate a difference between the delay amount of the delay circuit at the time of designing, and the actual delay value of the delay circuit.
By the way, Japanese Laid Open Patent Application (JP-P2000-201058A) discloses a semiconductor device. The semiconductor device of this conventional example is provided with a comparison delay circuit section, a reference delay circuit section, a delay time determining circuit section, and a delay adjustment circuit section. The comparison delay circuit section includes a delay circuit used to determine variations of delay time. The reference delay circuit section includes a delay circuit in which at least one given reference delay time is set as a reference value of delay time. The delay time determining circuit section determines the variations of delay time in the above comparison delay circuit section, based on the reference delay time of the reference delay circuit section. The delay adjustment circuit section having a plurality of delay circuits each having different sets delay time, selects one of the plurality of delay circuits in accordance with the determination result of the delay time determining circuit section, to delay a desired signal. Consequently, it is possible to determine the variations of delay time in the delay circuit caused by process variations and so on, and adjust the delay time in accordance with the variations.
Also, Japanese Laid Open Patent Application (JP-P2001-33529A) discloses a delay clock generating device for generating a delayed clock signal having a given delay amount. The delay clock generating device is provided with a period delay section, a half-period delay section, and a high-resolution delay section. The period delay section generates a delay amount corresponding to a reference clock period obtained by multiplying an integer number, the reference clock period being shorter than the given delay amount. The half-period delay section generates a delay amount of a half period of the reference clock signal. The high-resolution delay section adds a differential delay amount between the sum of delay amounts generated by the period delay section and the half-period delay section, and a given delay amount, to the delay amount generated by the period delay section and the half-period delay section. Consequently, it is possible to reduce a delay amount generated by the high-resolution delay section.
Also, Japanese Laid Open Patent Application (JP-P2002-76858A) discloses a timing signal generating circuit. The timing signal generating circuit of this conventional example is provided with a plurality of first delay elements, a first selecting section, a generating section, a second delay element, a detecting section, a comparing section, a specifying section, and a control section. The plurality of first delay elements are connected in series. The first selecting section selects one of the plurality of first delay signals outputted from the plurality of first delay elements. The generating section generates a timing signal based on the first delay signal selected by the first selecting section. The second delay element has the same delay characteristic as the first delay element. The detecting section detects N times (N is an integer number) of the delay time of the second delay element. The comparing section compares a detection time of the detecting section with a reference time. The specifying section specifies a value of the N where the detection time and the reference time are in a given relationship based on the comparing result of the detecting section. The control section controls the first selecting section to select the first delay signal that is relevant to a value specified by the specifying section. Consequently, it is possible to compensate a temperature dependency characteristic of a delay element.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 8-274602) discloses a variable delay circuit. The variable delay circuit of this conventional example is provided with a plurality of buses formed by serial connecting an optional number of variable delay gates, a bus selecting section, a reference delay time generating section, a phase comparing section, and a control signal generating section. The bus selecting section selectively connects the plurality of buses and sets a given delay time. The reference delay time generating section is arranged closely to the plurality of buses, and is formed by serially connecting the variable delay gates, which are the same variable delay gates used for the plurality of buses, and delays a reference clock signal by one period. The phase comparing section performs phase comparison of the reference clock signal and a delay output of the reference delay time generating section. The control signal generating section converts an output of the phase comparing section into a delay time control signal of the variable delay gate. The variable delay circuit simultaneously controls the variable delay gates of the reference delay time generating section in response to the delay time control signal. Consequently, it is possible to automatically compensate a variation of delay time caused by manufacturing variations.
Also, Japanese Laid Open Patent Application (JP-P2003-32104A) discloses a DLL circuit. The DLL circuit of this conventional example is provided with a basic phase comparator, a delay circuit, and a delay control circuit. The basic phase comparator detects a basic phase difference of two input signals. The delay control circuit receives an output signal of the basic phase comparator to adjust a delay amount of the delay circuit. The DLL circuit provides at least one phase comparator for detecting another phase difference different from the basic phase difference, and changes a change amount of a delay amount in accordance with the basic phase difference. Consequently, it is possible to reduce a time during which delay amounts converge (locked) at a desired delay value.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 9-304484) discloses a synchronous semiconductor memory device. The synchronous semiconductor memory device of this conventional example is provided with a reference delay circuit, a determining section, and a selecting section. The reference delay circuit receives an external synchronous signal, and outputs one or a plurality of delay signals for defining a delay design value. The determining section determines a position of a shift edge for defining a cycle time of the external synchronous signal, in comparison with a shift edge of one or a plurality of delay output signals of the reference delay circuit. The selecting section variably selects a delay value for delaying an internal clock signal in accordance with the magnitude relationship between an actual delay value and a design value of the delay circuit based on the determination result. The selecting section sets a delay value to shorter or longer side in accordance with the fact that a delay value of the reference delay circuit is larger or smaller than a design value, the delay value delaying the internal clock signal. Consequently, it is possible to automatically set a change in a delay value caused by process change at manufacturing, to an optimum value at the time of mode register setting of initial setting.